This application is related to U.S. patent application Ser. No. 09/085,039, pending "Integrated Flexible Interconnection" Attorney docket No. D/98249 (Common Assignee) filed concurrently herewith.
This Application is related to interconnection of integrated circuit chips and more particularly to fabrication of integrated flexible interconnects with a pitch less than 15 microns.
Due to the increasing demand for additional capacity or function on integrated circuit chips, the number of bonding pads and as a result, the number of interconnects of each chip needs to be increased. However, there is limited space at the edges of each chip. Therefore, in order to increase the number of the bonding pads, the pitch between the bonding pads needs to be decreased.
Conventional interconnection technologies such as wire bonding and tape automated bonding (TAB) are only capable of connecting bonding pads of pitch of 75 micron or above. The finest achievable pitch for Anisotropic conductive Film (AFC) is about 50 to 75 micron. Traditionally, flip chip technology is able to connect 5 micron bonding pads with a 25 micron pitch and a 7 micron bump height. Bump height is referred to the height of the solder bump (interconnect) on each bonding pad. Typically, the solder bumps are created by electroplating, electroless plating, or dip soldering. However, neither approach is capable of producing bump pitch less than 25 microns.
Referring to FIG. 1, there is shown a conventional tape 10 used in TAB process. Tape 10 which is made of polymer or polyimide has a plurality of patterned interconnects 12 which are typically made of copper with a layer of solder over the copper. Usually, a TAB process involves bonding the bonding pads of integrated circuit chips to patterned interconnects. Referring to FIG. 2, there is shown a tape 14 being placed over integrated circuit chips 16. Each one of the interconnects 18 is bonded to a bonding pad (not shown) on each chip 16 in the area shown as 20. The interconnects 18 in the area 20 are called inner leads and the bonding in the area 20 is called Inner Lead Bonding (ILB).
As can be observed, outside of the boundaries of each chip, the interconnects 18 fan out to facilitate the connection of the chip to the external circuitry. This is due to the fact that the external circuitry requires more space for connection. The interconnects 18 in the area 22 are called outer leads and the bonding in these areas are called Outer Lead Bonding (OLB).
In FIG. 2, once the inner leads 18 are bonded to the chips 16, the tape 14 will be cut along the lines 24. Therefore, each chip has bonded interconnects 18 which are flexible and extend beyond the boundaries of the chip. The fan out of the bonded interconnects 18 for the OLB requires a large area, which is not desirable for integrated circuits.
It is an object of this invention to fabricate an integrated circuit with integrated flexible interconnects with a pitch less than 15 microns.
It is also another object of this invention to eliminate the fan out of the interconnects to reduce surface area of the chip.